The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a contact structure in which a polycrystalline silicon wiring layer and an impurity region in a semiconductor substrate are connected via a metallic layer.
In the case where a polycrystalline silicon wiring layer and an impurity region are of the same conductivity type, ohmic connection can be made directly between the polycrystalline silicon wiring layer and the impurity region. However, in the case where a polycrystalline silicon wiring layer and an impurity region are of opposite conductivity type to each other, then direct connection cannot be made therebetween, and hence connection must be made via a metallic layer. Especially, in complementary insulated-gate field effect transistors (hereinafter called CMOS), a polycrystalline silicon wiring layer connected directly to a source or drain region of one of the transistors must be connected via a metallic layer to a source or drain of the other transistor.
In this case, if an aperture is formed in an insulating film covering the impurity region and the polycrystalline silicon wiring layer so as to overlap both the impurity region and the polycrystalline silicon wiring layer, and if a metallic layer is provided in this aperture to form a contact structure for bridging the impurity region and the polycrystalline silicon layer by being separately connected to the impurity region and the polycrystalline silicon wiring layer, then the arrangement is advantageous for realizing a high density in an integrated circuit because a wiring area can be made small. However, when the aperture is formed in the insulating film on the polycrystalline silicon wiring layer, an etching liquid such as hydrofluoric acid would penetrate through the grain boundaries of the polycrystalline silicon, resulting in generation of pin holes in an insulating film lying right under the polycrystalline silicon wiring layer, and consequently, there has been a problem that a leakage current is apt to occur between the substrate and the aforementioned conductor. Therefore, in a CMOS integrated circuit memory of 4 Kbits, for example, there exists a problem that an information holding current upon a stand-by state is greatly increased to several microamperes or several milliamperes as compared to about 10 nA or lower in a normal case.